ISR Interrupt Service Routine

ISR Interrupt Service Routine

ISR Interrupt Service Routine is the software(program) service it will execute  when interrupt will generates.When interrupt signal comes to micro controller controller will stop the its current execution and it will go to the interrupt vector table and it will get the address of ISR Interrupt Service Routine and it will execute ISR Interrupt Service Routine program and it will return back to main program.

AVR interrupt servicing 

1. In response to the interrupt, the CPU finishes any pending instructions 

    and then ceases fetching further instructions.  Global Interrupt Enable 

    (GIE) bit is cleared.

2. Hardware pushes the program counter on the stack.  

3. The CPU fetches the instruction from the interrupt vector table that 

    corresponds to the interrupt. This instruction is usually “jmp, address”. 

    The address is the address of the ISR.

00000000 <__vectors>:

   0:   0c 94 46 00     jmp     0x8c    ; 0x8c <__ctors_end>

   4:   0c 94 63 00     jmp     0xc6    ; 0xc6 <__bad_interrupt>

   8:   0c 94 63 00     jmp     0xc6    ; 0xc6 <__bad_interrupt>

   c:   0c 94 63 00     jmp     0xc6    ; 0xc6 <__bad_interrupt>

  10:   0c 94 63 00     jmp     0xc6    ; 0xc6 <__bad_interrupt>

  14:   0c 94 63 00     jmp     0xc6    ; 0xc6 <__bad_interrupt>

  18:   0c 94 63 00     jmp     0xc6    ; 0xc6 <__bad_interrupt>

  1c:   0c 94 63 00     jmp     0xc6    ; 0xc6 <__bad_interrupt>

  20:   0c 94 63 00     jmp     0xc6    ; 0xc6 <__bad_interrupt>

  24:   0c 94 63 00     jmp     0xc6    ; 0xc6 <__bad_interrupt>

  28:   0c 94 b4 02     jmp     0x568   ; 0x568 <__vector_10>

4. The CPU then begins to execute the ISR code. The first part of the ISR

     is compiler generated code that pushes the status register on the stack as 

     well as any registers that will be used in the ISR.

   

     From *.lst file:

/***********************************************************************/

//                          timer/counter 1 ISR                        

//When the TCNT1 compare1A interrupt occurs, port F bit 4 is toggled.  

//This creates the alarm sound from the clock.                         

/***********************************************************************/

ISR(TIM1_COMPA_vect){

 538:   1f 92           push    r1         ;save reg

 53a:   0f 92           push    r0         ;save reg

 53c:   0f b6           in      r0, 0x3f   ;put SREG into r0

 53e:   0f 92           push    r0         ;push SREG onto stack

 540:   11 24           eor     r1, r1     ;clear r1

 542:   8f 93           push    r24        ;save reg

 544:   9f 93           push    r25        ;save reg

 if (alarm_enable == 1)  //toggle port F.4 if button pushed

5. Just before the ISR is done, compiler generated code pops the saved

    registers as well as the status register.  Then the RETI instruction is 

    executed. This restores the program counter from the stack.  Global 

    Interrupt Enable bit gets set again.

 55a:   9f 91           pop     r25  ;restore regs

 55c:   8f 91           pop     r24  ;restore regs

 55e:   0f 90           pop     r0   ;put SREG back into r0

 560:   0f be           out     0x3f, r0 ;put r0 into SREG

 562:   0f 90           pop     r0   ;restore regs

 564:   1f 90           pop     r1   ;restore regs

 566:   18 95           reti

6. The CPU resumes executing the original instruction(main program) stream.