What is Interrupt latency? How do you measure interrupt latency? How to reduce the interrupt latency?

What is Interrupt latency? How do you measure interrupt latency? How to reduce the interrupt latency?

Answer: Interrupt latency is the time between interrupt request and execution of the first instruction of the ISR.

We need an oscilloscope or a logic state analyser. By entering the interrupt service routine (ISR), you need to activate an available port on your hardware (like a led port or so on) and deactivate it just before returning from the ISR. You can do that by writing the appropriate code.

By connecting one input of the oscilloscope (or logic state analyser) to the INTR pin of the microprocessor and the second one to the port you activate/deactivate, you can measure the latency time and the duration of the ISR

Causes of interrupt latencies

•  The first delay is typically in the hardware: The interrupt request signal needs to be synchronised to the CPU clock. Depending on the synchronisation logic, typically up to 3 CPU cycles can be lost before the interrupt request has reached the CPU core.
•  The CPU will typically complete the current instruction. This instruction can take a lot of cycles; on most systems, divide, push-multiple or memory copy instructions are the instructions which require most clock cycles. On top of the cycles required by the CPU, there are in most cases additional cycles required for memory access. In an ARM7 system, the instruction STMDB SP!,{R0-R11,LR}; Push parameters and perm. Registers are typically the worst case instruction. It stores 13 32-bit registers on the stack. The CPU requires 15 clock cycles. The memory system may require additional cycles for wait states.
• After completion of the current instruction, the CPU performs a mode switch or pushes registers (typically PC and flag registers) on the stack. In general, modern CPUs (such as ARM) perform a mode switch, which requires fewer CPU cycles than saving registers.
• Pipeline fill: Most modern CPUs are pipelined. Execution of an instruction happens in various stages of the pipeline. An instruction is executed when it has reached its final stage of the pipeline. Since the mode switch has flushed the pipeline, a few extra cycles are required to refill the pipeline.