Automotive Interview Questions

Automotive Interview Questions and CAN interview questions and important C programming interview Questions are asked in Automotive interviews.This are the very important questions for automotive interviews. 

<<can Interview Questions

1.What is the difference between declaration and definition?

Answer: Definition means where a variable or function is defined in reality and actual memory is allocated for variable or function.

Declaration means just giving a reference of a variable and function.

3.What is interrupt?

 Answer: Interrupts (also known as traps or exceptions in some processors) are a technique of diverting the processor from the execution of the current program so that it may deal with some event that has occurred. Such an event may be an error from a peripheral, or simply that an I/O device has finished the last task it was given and is now ready for another. An interrupt is generated in your computer every time you type a key or move the mouse. You can think of it as a hardware-generated function call.

 4.What is Hardware Interrupt?

Answer:There are two ways of telling when an I/O device (such as a serial controller or a disk controller) is ready for the next sequence of data to be transferred. The first is busy waiting or polling, where the processor continuously checks the device’s status register until the device is ready. This wastes the processor’s time but is the simplest to implement. For some time-critical applications, polling can reduce the time it takes for the processor to respond to a change of state in a peripheral.

5.What is Software Interrupt?

Answer: A software interrupt is generated by an instruction. It is the lowest-priority interrupt and is generally used by programs to request a service to be performed by the system software (operating system or firmware).

5.Difference between Hardware Interrupt and Software Interrupt?

6. What is Interrupt latency? How do you measure interrupt latency? How to reduce the interrupt latency?

7.  Vonneuman and harvard architecture differences?

Answer: The name Harvard Architecture comes from the Harvard Mark I relay-based computer. The most obvious characteristic of the Harvard Architecture is that it has physically separate signals and storage for code and data memory. It is possible to access program memory and data memory simultaneously. Typically, code (or program) memory is read-only and data memory is read-write. Therefore, it is impossible for program contents to be modified by the program itself.

The vonneumann Architecture is named after the mathematician and early computer scientist John von Neumann. von Neumann machines have shared signals and memory for code and data. Thus, the program can be easily modified by itself since it is stored in read-write memory.

Harvard architecture has separate data and instruction busses, allowing transfers to be performed simultaneously on both buses. Von Neumann architecture has only one bus which is used for both data transfers and instruction fetches, and therefore data transfers and instruction fetches must be scheduled – they cannot be performed at the same time.

It is possible to have two separate memory systems for a Harvard architecture. As long as data and instructions can be fed in at the same time, then it doesn’t matter whether it comes from a cache or memory. But there are problems with this. Compilers generally embed data (literal pools) within the code, and it is often also necessary to be able to write to the instruction memory space, for example in the case of self modifying code, or, if an ARM debugger is used, to set software breakpoints in memory. If there are two completely separate, isolated memory systems, this is not possible. There must be some kind of bridge between the memory systems to allow this.

Using a simple, unified memory system together with a Harvard architecture is highly inefficient. Unless it is possible to feed data into both buses at the same time, it might be better to use a von Neumann architecture processor.

Use of caches

At higher clock speeds, caches are useful as the memory speed is proportionally slower. Harvard architectures tend to be targeted at higher performance systems, and so caches are nearly always used in such systems.

Von Neumann architectures usually have a single unified cache, which stores both instructions and data. The proportion of each in the cache is variable, which may be a good thing. It would in principle be possible to have separate instruction and data caches, storing data and instructions separately. This probably would not be very useful as it would only be possible to ever access one cache at a time.

Caches for Harvard architectures are very useful. Such a system would have separate caches for each bus. Trying to use a shared cache on a Harvard architecture would be very inefficient since then only one bus can be fed at a time. Having two caches means it is possible to feed both buses simultaneously….exactly what is necessary for a Harvard architecture.

This also allows to have a very simple unified memory system, using the same address space for both instructions and data. This gets around the problem of literal pools and self modifying code. What it does mean, however, is that when starting with empty caches, it is necessary to fetch instructions and data from the single memory system, at the same time. Obviously, two memory accesses are needed therefore before the core has all the data needed. This performance will be no better than a von Neumann architecture. However, as the caches fill up, it is much more likely that the instruction or data value has already been cached, and so only one of the two has to be fetched from memory. The other can be supplied directly from the cache with no additional delay. The best performance is achieved when both instructions and data are supplied by the caches, with no need to access external memory at all.

This is the most sensible compromise and the architecture used by ARMs Harvard processor cores. Two separate memory systems can perform better, but would be difficult to implement

8.     RISC and CISC differences?

Answer:

CISC: (Complex Instruction Set Computer)

Eg: Intel and AMD CPU’s

• CISC chips have a large amount of different and complex instructions.
• CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions.
• CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of operations.
• In CISC, compiler has to do very little work to translate a high-level language statement into assembly. Because the length of the code is relatively short, very little RAM is required to store instructions. The emphasis is put on building complex instructions directly into the hardware.
• When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate register.

RISC: (Reduced Instruction Set Computer)

Eg: Apple, ARM processors

• Fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructions. However, more instructions are needed to accomplish a task.
• RISC chips require fewer transistors, which makes them easier to design and cheaper to produce.
• it’s easier to write powerful optimized compilers, since fewer instructions exist.
• RISC is cheaper and faster.
• RISC puts a greater burden on the software. Software needs to become more complex. Software developers need to write more lines for the same tasks. Therefore they argue that RISC is not the architecture of the future, since conventional CISC chips are becoming faster and cheaper
• Simple instructions that can be executed within one clock cycle.
• “MULT” command described above could be divided into three separate commands: “LOAD,” which moves data from the memory bank to a register, “PROD,” which finds the product of two operands located within the registers, and “STORE,” which moves data from a register to the memory banks.
• At first, this may seem like a much less efficient way of completing the operation. Because there are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language statement into code of this form.
• Separating the “LOAD” and “STORE” instructions actually reduces the amount of work that the computer must perform.
• Major problem of RISC – they don’t afford the widespread compatibility, that x86 chips do.

	CISC		RISC
	Emphasis on hardware		Emphasis on software
	Includes multi-clock complex instructions		Single-clock, reduced instruction only
	Memory-to-memory: “LOAD” and “STORE” incorporated in instructions		Register to register: “LOAD” and “STORE” are independent instructions
	Small code sizes, high cycles per second		Low cycles per second, large code sizes
	Transistors used for storing complex instructions		Spends more transistors on memory registers
CISC		RISC
Complex instructions require multiple cycles		Reduced instructions take 1 cycle
Many instructions can reference memory		Only Load and Store instructions can reference memory
Instructions are executed one at a time		Uses pipelining to execute instructions
Few general registers		Many general registers

9.     What are the startup code steps?

Answer:

1. Disable all the interrupts.
2. Copy and initialized data from ROM to RAM.
3. Zero the uninitialized data area.
4. Allocate space and for initialize the stack.
5. Initialize the processor stack pointer
6. Call main

10.     What are the booting steps for a CPU?

Answer:

• The power supply does a self check and sends a power-good signal to the CPU.

The CPU starts executing the code stored in ROM on the motherboard starts the address 0xFFFF0.

• The routines in ROM test the central hardware, search for video ROM, perform a checksum on the video ROM and executes the routines in video ROM.
• The routines in the mother board ROM then continue searching for any ROM, checksum and executes these routines.
• After performing the POST (Power On-Self Test) is executed. The system will search for a boot device.
• Assuming that the valid boot device is found, IO.SYS is loaded into memory and executed. IO.SYS consists primarily of initialization code and extension to the memory board ROM BIOS.
• MSDOS.SYS is loaded into memory and executed. MSDOS.SYS contains the DOS routines.
• CONFIG.SYS (created and modified by the user. load additional device drivers for peripheral devices), COMMAND.COM (It is command interpreter- It translates the commands entered by the user. It also contains internal DOS commands. It executes and AUTOEXEC.BAT), AUTOEXEC.BAT (It contains all the commands that the user wants which are executed automatically every time the computed is started).

11. What Little-Endian and Big-Endian? How can I determine whether a machine’s byte order is big-endian or little endian? How can we convert from one to another?

 First of all, Do you know what Little-Endian and Big-Endian mean?
Little Endian means that the lower order byte of the number is stored in memory at the lowest address, and the higher order byte is stored at the highest address. That is, the little end comes first.
For example, a 4 byte, 32-bit integerByte3 Byte2 Byte1 Byte0will be arranged in memory as follows:Base_Address+0 Byte0
Base_Address+1 Byte1
Base_Address+2 Byte2
Base_Address+3 Byte3Intel processors use “Little Endian” byte order.”Big Endian” means that the higher order byte of the number is stored in memory at the lowest address, and the lower order byte at the highest address. The big end comes first.Base_Address+0 Byte3
Base_Address+1 Byte2
Base_Address+2 Byte1
Base_Address+3 Byte0Motorola, Solaris processors use “Big Endian” byte order.In “Little Endian” form, code which picks up a 1, 2, 4, or longer byte number proceed in the same way for all formats. They first pick up the lowest order byte at offset 0 and proceed from there. Also, because of the 1:1 relationship between address offset and byte number (offset 0 is byte 0), multiple precision mathematic routines are easy to code. In “Big Endian” form, since the high-order byte comes first, the code can test whether the number is positive or negative by looking at the byte at offset zero. Its not required to know how long the number is, nor does the code have to skip over any bytes to find the byte containing the sign information. The numbers are also stored in the order in which they are printed out, so binary to decimal routines are particularly efficient. Here is some code to determine what is the type of your machine.

int num = 1;
if(*(char *)&num == 1)
{
printf(“\nLittle-Endian\n”);
}
else
{
printf(“Big-Endian\n”);
}And here is some code to convert from one Endian to another.int myreversefunc(int num)
{
int byte0, byte1, byte2, byte3;byte0 = (num & x000000FF) >> 0 ;
byte1 = (num & x0000FF00) >> 8 ;
byte2 = (num & x00FF0000) >> 16 ;
byte3 = (num & xFF000000) >> 24 ;return((byte0 << 24) | (byte1 << 16) | (byte2 << 8) | (byte3 << 0));
}

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